University of Portland Bulletin 2013-2014

EE 435 Verilog Digital Systems Modeling

Introduction to Verilog-based design process. Hierarchical modeling methodology. Basic Verilog language structures for modeling digital hardware functions. Modules and ports. Gate-level modeling. Data flow modeling. Behavioral modeling. Tasks and functions. Useful modeling techniques in digital system design. Component timing and delay modeling. Logic synthesis with Verilog HDL.

Prerequisite

EE 231 or equivalent.
  • Up one level
  • 400