EE 535 Verilog Digital Systems Modeling

Verilog-based design process. Hierarchical modeling methodology. Basic Verilog language structures for modeling digital hardware functions. Modules and ports. Gate level modeling. Dataflow modeling. Behavioral modeling. Tasks and functions. Useful modeling techniques in digital system design. Component timing and delay modeling. Logic synthesis with Verilog HDL. Advanced topics on high-level synthesis and system verification.